1. Technical Field
The present invention relates generally to a method for manufacturing a semiconductor device and, more particularly, to methods for forming trench isolations.
2. Discussion of the Related Art
As semiconductor devices become more highly integrated, the size of a unit cell is reduced, thereby reducing an area occupied by an isolation region in the unit cell. Accordingly, for the isolation region, a trench isolation having a reduced width and not having a bird's beak phenomenon is used. As the width of the trench isolation decreases, an aspect ratio of a trench increases, thereby making it difficult to fill the trench with a dielectric material without a void.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method of forming a trench isolation.
With reference to FIG. 1A, a polish stop layer pattern 30 is formed over a substrate 10, and the substrate 10 is etched by using the polish stop layer pattern 30 as a mask. Here, trenches with different widths, i.e. a narrow width trench 13 and a wide width trench 15, are formed in the substrate 10. A gate dielectric layer 20 is formed between the polish stop layer pattern 30 and the substrate 10.
Next, the trenches 13, 15 are filled with a high-density plasma (hereinafter, referred to as “HDP”) CVD oxide layer 40. Generally, the HDP-CVD oxide layer has improved gap-filling properties over a conventional PECVD (Plasma Enhanced Chemical Vapor Deposition) oxide layer because of the repetitive deposition and sputter etching steps used in the formation of the HDP CVD oxide layer. However, during the sputter etching process, the oxide layer sputtered from sidewalls of the trenches 13, 15 is re-deposited on an opposite sidewall. For instance, with respect to the wide width trench 15, the oxide layer is re-deposited on the entire opposite sidewall. While for the narrow width trench 13, the oxide layer is re-deposited on an upper portion of the opposite sidewall. Therefore, an oxide layer 40a formed on the upper portion of sidewalls of the narrow width trench 13 is thicker than an oxide layer 40b formed on the upper portion of the sidewalls of the wide width trench 15. Moreover, when the thick oxide layers 40a formed on the upper portion of the sidewalls of the narrow width trench 13 meet each other, the inside of the trench cannot be completely filled with the oxide layer, and a void V is formed within the narrow width trench 13.
With reference to FIG. 1B, to completely fill the narrow width trench 13 without a void, an entrance of the narrow width trench 13 is widen by wet etching the oxide layer (40a in FIG. 1A) formed on the upper portion of the sidewalls of the narrow width trench 13. Since the wet etching is performed over the entire substrate, the oxide layer (40b in FIG. 1A) formed of an upper portion of the sidewalls of the wide width trench 15 and the gate dielectric layer 20 adjacent to the wide width trench 15 are also etched, thereby forming an undercut 25. Subsequently, an oxide layer 50 is deposited to completely fill the trenches 13, 15. However, the oxide layer 50 is not deposited within the undercut 25, thereby forming a void. The void 25 and the undercut gate dielectric layer impede reliability of a semiconductor device.
U.S. Pat. No. 6,531,377 discloses a method for manufacturing an isolation comprising the steps of forming a first dielectric layer on a substrate and sidewalls of a trench, performing an isotropic etch to remove the dielectric layer on the trench sidewalls, followed by forming a second dielectric layer. However, performing the isotropic etch over the entire substrate can cause the above-mentioned problems.
Therefore, a need exists for methods of forming trench isolations that prevent an undercut from forming in a gate dielectric layer adjacent to a trench isolation and voids from forming in the trench isolation.